Memory systems can employ memory devices to store and access information. The memory devices can include volatile memory devices, non-volatile memory devices, or a combination device. Memory devices, such as dynamic random-access memory (DRAM), can utilize electrical energy to store and access data. The memory devices can include Double Data Rate (DDR) RAM devices that implement DDR interfacing scheme (e.g., DDR4, DDR5, etc.) for high-speed data transfer.
FIG. 1 illustrates a block diagram of a memory device 100 (e.g., a DRAM device) that utilize electrical energy to store and access data. For example, the memory device 100 can include memory banks 102 that are organized/configured according to one or more bank groups 104. Each of the bank groups 104 can include a set of two or more memory banks 102. In some embodiments, each of the bank groups 104 can include a set of four or eight memory banks 102.
The memory device 100 can further include an input/output (I/O) circuit 106 configured to communicate data (e.g., DQ, RDQS, DBI, DMI, etc.), command, and/or address signals. In some embodiments, the I/O circuit 106 can include circuits (e.g., receivers, pads, etc.) configured to process a first data unit 112 (e.g., an upper byte of data), a second data unit 114 (e.g., a lower byte of data), etc. For example, the memory device 100 may communicate the data in units of 64 or 128 bits. The first data unit 112 can include an upper portion (e.g., an upper nibble, an upper byte, an upper word/half, etc.) of the 64/128 bit data units. The second data unit 114 can include a lower portion (e.g., a lower nibble, a lower byte, a lower word/half, etc.) of the 64/128 bit data units. Also, the “upper” and the “lower” portions can correspond to a bit order, such as corresponding to most significant bit(s) and the least significant bit(s), respectively. The first data unit 112 and the second data unit 114 can include non-overlapping portions of the communicated data unit.
In some embodiments, the I/O circuit 106 can include a command-address decoder 316. The command-address decoder 116 can be configured to process commands and/or addresses. For example, the command-address decoder 116 can process the address signal, such as by supplying a decoded row address signal (XADD) and/or a decoded column address signal (YADD), supplying the bank address signal (BADD), etc. to corresponding decoders. Also, the command-address decoder 116 can process commands and generate various internal signals/commands for performing memory operations.
The communicated data, command, address, etc. can be routed to/from the corresponding location (e.g., the particular/designated set of data cells). In some embodiments, the I/O circuit 106 can include a center hub 122, bank logics 124, etc. The center hub 122 can be configured to perform the bank group or group-level control. The bank logic circuits 124 can be configured to perform the bank-level control. The center hub 122, the bank logic circuitry 124, etc. can include a set of drivers (e.g., one-directional drivers and/or bi-directional drivers) for communicating the data with the memory banks 102.
The center hub 122 and/or the bank logic circuits 124 can perform the control operations according to one or more clock/timing signals. For example, the memory device 100 (e.g., the center hub 122 and/or the bank logic circuits 124) can utilize a global driver clock signal, a global multiplexer clock signal, one or more group driver clock signals, etc.
FIG. 2 illustrates a timing diagram 200 of a memory device (e.g., the memory device 100 of FIG. 1). The timing diagram 200 can illustrate a relationship between a global clock signal 202 (e.g., the global driver clock signal, the global multiplexer clock signal, etc.) and one or more local/sectional (e.g., bank-level and/or bank group-level) clock signals, such as a first group clock signal 204, a second group clock signal 206, etc.
The global clock signal 202 can be an overall timing signal configured to coordinate multiple different drivers/multiplexers in the memory device 100. The memory device 100 can generate the local/sectional clock signals to control operations at individual sections (e.g., at the individual bank-group or bank). For example, the first group clock signal 204 can control operations (e.g., operations for a driver, a multiplexer, a routing circuit, a buffer, other components, etc.) for a first bank group (e.g., BG0) or a first memory bank. Also, the second group clock signal 206 can control operations for a second bank group (e.g., BG1) or a second memory bank. The local/sectional clock signals can be aligned with the global clock signal 202. In some embodiments, the local/sectional clock signals can be contemporaneous with every other clock pulses 212 in the global clock signal 202. As such, a global clock period 214 can be shorter than a local clock period 216. Also, the local clock period 216 can be a multiple (e.g., double) of the global clock period 214.
The timing diagram 200 can perform the memory operations (e.g., write) to the memory bank/cells during a processing duration 218. The processing duration 218 can include a set of pulses or periods (e.g., a quantity of global clock signals 202 and a different quantity of the local clock periods 216, etc.). For example, the processing duration 218 can include four pulses and four clock periods 214 for processing one or more bytes.
While each of the clock pulses and the corresponding voltage transitions (e.g., edges), the pulses/transitions also consume power. Further, with technological advancements in other areas and increasing applications, the market is continuously looking for faster and more efficient devices. To meet the market demand, the semiconductor devices are being pushed to the limit. As the signal/processing rates increase, the clock pulses may consume increasing amounts of power. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the desire to differentiate products in the marketplace, it is increasingly desirable that answers be found to these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater pressure to find answers to these problems.